. Proficient in Verilog coding and RTL design, data path designs, 2. Knowledge of RTL checks ex
- LINT, SDC, CDC 3. Familiar with synthesis flow and timing constraints 4. Experience in writing Verilog testbench and running simulations. 5. Familiar with any of the interface Protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display
📌 Lead RTL Design Engineer (New Delhi)
🏢 Cadence System Design and Analysis
📍 New Delhi
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