Responsibilities:
Person will be responsible for scan insertion, stuck_at & at-speed ATPG, scan simulations and post silicon debugging for hierarchical design. Skill
Requirements:
Person should have good hands-on experience in SCAN, ATPG , Scan pattern verification and also should have good understanding of scan constraints. Valuable to have: Knowledge of MBIST.
Experience:
5
- 10 yrs
Qualifications:
B.
Tech/M.
Tech B.
Tech/B.
E/M.
Tech/M.
E Skills DFT, Hierarchical Design, Post-Silicon Validation
📌 Associate III (Bengaluru)
🏢 UST
📍 Bengaluru
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