Job highlights

- Bachelors or Masters degree in computer engineering / Electrical Engineering with minimum 8-10 years of experience.

- Prior experience with 3nm or finer geometries is a plus. Proficient use of tcl / Perl. Must have good communication skills and self-driven individual. .

Job Summary The focus of this role is to plan and execute full chip timing activities and signoff for advanced chiplets in latest technologies.

Key Responsibilities

- Fullchip Timing analysis for multiple modes that includes Functional and DFT and interface special timing checks
- To have expertise in understanding and debugging timing issues in Fullchip level and block level

- Experience on Floor-planning, Place route, power and clock distribution, pin placement

- Role involves interaction with multiple design teams, CAD teams, Tool vendors, (on and cross sites)

- In-depth knowledge on industry leading tools like Primetime and ICC2

- Knowledge of Synthesis and DFT is added advantage

- Knowledge of constraints analysis using GCA or similar tool is added advantage





- Prior experience with 3nm or finer geometries is a plus

- Proficient use of tcl/Perl

- Must have valuable communication skills and self-driven individual

Qualifications

- Bachelors or Masters degree in computer engineering/Electrical Engineering with minimum 8-10 years of experience

Requirements

- You have a passion for physical design and STA in general.

- You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones.

- You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Sr PD Engineer - STA & Timing Closure (Hyderabad)
🏢 Advanced Micro Devices (AMD)
📍 Hyderabad