We are looking for skilled Layout Engineers with recent hands-on experience on advanced technology nodes to work with a leading global semiconductor client. You will design and deliver high-quality layouts for critical analog, mixed-signal and custom digital blocks, and support full-chip integration.
Key Responsibilities
- Design and develop layouts for critical analog, mixed-signal and custom digital blocks
- Support full-chip level integration
- Deliver block-level layouts on time, to acceptable quality standards
- Run and close physical verification checks: LVS, DRC, DFM, Antenna and EMIR
- Work with circuit design and other cross-functional teams to resolve layout and verification issues
- Work independently with minimal supervision and keep stakeholders updated on progress
Mandatory Requirements
- 4 to 6 years of relevant layout experience
- Hands-on experience on TSMC 3nm, with a minimum of 3 to 6 months of real-time project experience
- Expertise in Cadence Virtuoso VLE/VXL
- Expertise in Siemens (Mentor Graphics) Calibre DRC/LVS
- Experience with LVS, DRC, DFM, Antenna check and EMIR flows
- BE/BTech or MTech in Electronics / VLSI Engineering
- Positive written and verbal communication skills
- Ability to work independently
- Available to attend an in-person interview in Hyderabad
- Notice period of 15 days or less
Preferred Skills
- Experience on other TSMC nodes (16/12nm, 7nm, 5nm) or other foundries (Intel, Samsung, GlobalFoundries)
- Recent hands-on experience on lower nodes
- HBM layout experience (added advantage)
- Layout exposure to analog blocks such as regulators, charge pumps and power management
📌 Analog Layout Engineer (Secunderabad)
🏢 3iTech Global Private
📍 Secunderabad
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