Job Summary

Perform Power Integrity (PI) simulationsConduct package and board layout power analysisExecute PIBOM analysisGenerate S-parameter modelsDevelop reusable PI modelsAnalyze simulation results and provide recommendationsGenerate engineering reports and supporting documentationCreate customer-facing engineering collateral where requiredSupport development of PIER and Platform Design Guide contentParticipate in technical discussions with Intel engineering teams

Key Responsibilities

Power Integrity (PI) analysis experienceHSPICECadence Sigrity PowerDCCadence PowerSIPackage power delivery analysisBoard power delivery analysisS-parameter generation and analysisSignal/Power simulation methodologyEngineering documentation and reporting

Skill Requirements

Semiconductor industry experienceCustomer platform design experienceExperience supporting CPU, package, or board development programsFamiliarity with Platform Design Guides

Must Have Skill

Cadence

Valuable to Have Skill

Other Requirements

📌 Senior Design Lead (Mysuru)
🏢 HCLTech
📍 Mysuru