Description Invent the future with us. Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AIcompute. As a pioneer in the current frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications. Join us at Ampere and work alongside a passionate and growing team
- we’d love to have you apply

About the role
We are seeking a hands-on Principal Firmware Engineer to lead the architecture, design, development, integration, and validation of low-level firmware for high-speed Ethernet solutions, including Gigabit MAC/PCS/PHY-adjacent interfaces, PTP/gPTP timing, TSN features, DMA, QoS, and platform drivers. This role requires a technically strong engineer who can operate at both system and register level: define firmware architecture, develop production-quality drivers, diagnose hardware/software issues on silicon, guide firmware engineers, and collaborate closely with RTL, verification, silicon validation, applications, and customers. The successful candidate will own critical aspects of the Ethernet firmware stack from boot-time initialization through high-throughput data-path operation, time synchronization, traffic scheduling, error handling, diagnostics, and performance characterization. What you’ll achieve: Technical Architecture and Ownership
• Define firmware architecture for high-speed Ethernet subsystems supporting high speed gigabit Ethernet modes.
• Lead design of low-level drivers for Ethernet MAC, DMA, PCS, SerDes/PHY control interfaces, MDIO, interrupt controllers, clock/reset, and associated IP blocks.
• Define scalable driver state machines for initialization, configuration, link management, normal operation, diagnostics, fault recovery, and reset handling.
• Establish firmware interfaces and configuration models for Ethernet QoS, PTP, TSN, packet classification, DMA queues, and traffic scheduling.
• Identify hardware/software integration risks early and influence hardware architecture, register design, diagnostics, and verification requirements.
• Design firmware for high-throughput and low-latency operation for Gigabit Ethernet.
• Analyze and optimize CPU utilization, DMA bandwidth, memory bandwidth, interrupt load, cache behavior, and buffer utilization.
• Drive root-cause analysis for packet loss, descriptor corruption, DMA stalls, RX starvation, TX underflow, FIFO overflow, bus errors, and performance regressions.
• Ensure correct cache-coherency and memory-ordering behavior on Arm-based SoCs with coherent or non-coherent DMA. PTP / gPTP / Time Synchronization
• Develop and integrate firmware support for hardware timestamping and IEEE 1588 PTP / IEEE 802.1AS gPTP.




• Configure and manage PTP clocks, timestamp units, clock adjustment, rollover handling, and TX/RX timestamp correlation.
• Support synchronization applications requiring deterministic timing and bounded timestamp latency.
• Develop diagnostics and performance characterization for time synchronization accuracy, offset, drift, jitter, timestamp loss, and synchronization recovery.
• Collaborate with system/software teams on PTP stack integration and time-domain requirements. TSN and Ethernet QoS
• Lead firmware enablement for relevant TSN and QoS capabilities
• Define queue allocation, scheduling, buffer, and congestion-management policies for mixed traffic environments.
• Develop traffic test scenarios to validate latency, jitter, throughput, packet loss, fairness, and isolation under congested conditions. Bring-Up, Debug, and Validation
• Lead pre-silicon and post-silicon firmware bring-up for Ethernet subsystems.
• Debug complex hardware/firmware interactions
• Develop fault-injection and negative-test scenarios
• Drive technical resolution of customer and field escalations. Leadership and Collaboration
• Provide technical leadership and mentorship to firmware engineers.
• Lead architecture reviews, code reviews, debug reviews, and design-for-testability discussions.
• Establish reusable driver frameworks, coding patterns, debug utilities, and test infrastructure.
• Work closely with RTL, design verification, validation, software, systems, security, safety, product, and customer engineering teams.
• Guide junior and senior engineers toward independent ownership of firmware subsystems.
• Communicate technical risks, design choices, trade-offs, and milestones clearly to engineering leadership and cross-functional stakeholders. About you:
• Bachelor's degree with 8 years or Master’s degree with 6 years of experience in embedded firmware, device-driver, networking, or semiconductor software development experience
• Proven hands-on experience developing low-level drivers for Ethernet MAC, DMA, PHY/PCS control, networking accelerators, or comparable high-performance peripheral IP.
• Strong understanding of Ethernet fundamentals including Ethernet frame format; MAC and PHY operation; VLAN / IEEE 802.1Q; QoS / 802.1p; link negotiation and management; MDIO/MDC; flow control; multicast and filtering.
• Strong experience with DMA architectures




• Strong understanding of embedded C/C++ and low-level programming concepts:
• Strong Arm SoC knowledge of Cortex-A, Cortex-R, Cortex-M;
• Experience with IEEE 1588 PTP, gPTP, hardware timestamping, or time synchronization systems.
• Demonstrated ability to debug difficult system issues using hardware and software observability tools.
• Ability to lead technical design and influence teams across firmware, RTL, verification, and validation.
• Strong written and verbal communication skills. Preferred Qualifications
• Experience with 25GbE, 10GbE, 40GbE, 50GbE, or other high-speed Ethernet MAC/PCS/SerDes-based systems.
• Experience with TSN features including IEEE 802.1Qav, 802.1Qbv, 802.1Qbu, 802.1Qci, IEEE 802.3br, and IEEE 802.1AS.
• Experience with Ethernet MACsec / IEEE 802.1AE, MKA, replay protection, secure association management, or secure networking.
• Experience with high-speed packet test equipment, traffic generators, packet analyzers, and performance benchmarking.
• Experience with FPGA prototyping, emulation, pre-silicon firmware development, or post-silicon validation. What we’ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, cash long-term incentive, and comprehensive benefits. Benefits highlights include:
• Premium medical, dental, vision insurance, parental benefits includingcrechereimbursement, as well as a retirement plan,so thatyou can feel secure in your health,financial futureand child care during work.
• Generous paid time off policy so that you can embrace a healthy work-life balance
• Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And thereismuch more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are excited to share more about our career opportunities with you through the interview process. We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us. Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.

📌 Principal Firmware Engineer, High-Speed Ethernet (Pune)
🏢 Ampere
📍 Pune