Role & responsibilities

1. Analog & Mixed-Signal Layout Design

- Design and develop full-custom analog, mixed-signal and custom digital layouts.
- Create transistor-level layouts based on schematics and design specifications.
- Handle analog blocks such as Op-Amps, LDOs, Regulators, Charge Pumps, PLLs, BGRs, ADCs and Current Mirrors.

2. Advanced Technology Node Experience

- Work on advanced semiconductor technology nodes such as TSMC 3nm, 5nm, 7nm, 12nm and 16nm.
- Develop and optimize layouts using FinFET technology.
- Understand process-specific design rules and advanced-node layout constraints.

3. Floor Planning, Placement & Routing

- Perform block-level floor planning, device placement and critical signal routing.
- Apply matching techniques such as Common Centroid and Interdigitation.
- Implement shielding, guard rings and power routing.
- Optimize layout area, parasitics, signal integrity and performance.

4. Physical Verification & Signoff

- Perform physical verification using:

- DRC (Design Rule Check)
- LVS (Layout Versus Schematic)
- DFM (Design for Manufacturability)
- Antenna Checks
- ERC (Electrical Rule Check)
- EM/IR (Electromigration and IR Drop)

- Identify and resolve physical verification violations.
- Ensure layouts meet foundry requirements and are signoff-ready.

5. EDA Tools & Technology

- Hands-on experience with Cadence Virtuoso Layout Editor (VLE/VXL).
- Experience with Mentor Graphics Calibre for DRC/LVS verification.




- Work with foundry PDKs, technology files and design rule decks.

6. Layout Optimization & Debugging

- Analyze and resolve layout-related issues involving parasitics, electromigration, antenna effects, latch-up and density.
- Optimize layout for area, power, performance and reliability.
- Perform ECO (Engineering Change Order) implementation and layout modifications.

7. Block-Level & Full-Chip Integration

- Support analog and mixed-signal IP integration.
- Coordinate with circuit designers, physical verification teams and top-level integration teams.
- Ensure successful block-level layout delivery and full-chip integration support.

8. Independent Execution & Delivery

- Independently manage layout assignments from floor planning through physical verification.
- Deliver high-quality layouts within project timelines.
- Review layouts and resolve technical issues with minimal supervision.

9. Documentation & Collaboration

- Maintain layout documentation, verification reports and design updates.
- Collaborate with cross-functional engineering teams.
- Communicate project progress, technical challenges and delivery status.

Preferred candidate profile

- TSMC 3nm / 5nm advanced-node layout experience.
- Hands-on experience with HBM (High Bandwidth Memory).
- Analog blocks such as Regulators, Charge Pumps and Power Management.
- Experience with Intel, Samsung and GlobalFoundries technologies.

📌 Analog Custom Layout Engineer (Hyderabad)
🏢 Kotson It Solutions
📍 Hyderabad