Role & responsibilities

- Perform end-to-end Physical Design implementation of ASIC designs.
- Work on advanced technology nodes, including 3nm, 5nm, and 7nm.
- Perform block-level floorplanning, power planning, placement, clock tree synthesis (CTS), and routing.
- Conduct IR Drop analysis and address power integrity issues.
- Perform block-level timing analysis, timing closure, and optimization.
- Ensure timing closure through effective setup and hold violation fixing.
- Coordinate with cross-functional teams to resolve design and implementation challenges.
- Perform timing sign-off and STA (Static Timing Analysis) closure.
- Ensure design meets PPA (Power, Performance, and Area) targets.

Preferred candidate profile

- Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering, or a related field.
- Minimum 3+ years of experience in ASIC Physical Design.
- Strong understanding of Physical Design methodology and implementation flow.
- Hands-on experience with 7nm,



10nm, and/or 14nm technology nodes.
- Good knowledge of block-level floorplanning and IR Drop analysis.
- Experience in placement, Clock Tree Synthesis (CTS), routing, and timing closure.
- Proficiency in STA, timing analysis, and sign-off methodologies.
- Strong problem-solving, analytical, and debugging skills.
- Positive communication skills and ability to work effectively in a team.

Perks and benefits

- Opportunity to work on advanced semiconductor technology nodes.
- Exposure to end-to-end ASIC Physical Design methodologies.
- Opportunity to work on challenging VLSI projects and cutting-edge technologies.
- Collaborative and technically driven work environment.
- Opportunities for continuous learning and professional growth.
- Career development opportunities in the semiconductor and VLSI domain.

📌 Physical Design Engineer (Hyderabad)
🏢 InSemi Technology Services
📍 Hyderabad