Senior AMS Verification Engineer Analog & Mixed Signal (Bengaluru)

Senior AMS Verification Engineer Analog & Mixed Signal (Bengaluru)

05 Nov
|
TheKnowledgeHive
|
Bengaluru

05 Nov

TheKnowledgeHive

Bengaluru

Job Title: Senior AMS Verification Engineer – Analog & Mixed Signal

Location: Bengaluru

Experience: 10+ years

CTC: Up to ₹50 LPA

Industry: Semiconductor

Department: VLSI Design & Verification / Design Enablement

Job Summary

We are seeking an experienced Analog Mixed-Signal (AMS) Verification Engineer to support functional and parametric verification of semiconductor designs. The role involves AMS behavioural modelling, UVM testbench development, simulation, regression management, CAD methodology optimization and Design Engineering support.

Key Responsibilities

- Develop and execute functional and parametric verification plans for analog and mixed-signal IPs and systems.
- Develop, validate and maintain behavioural models using Wreal, SystemVerilog and Verilog-AMS.
- Build and enhance UVM-based verification environments and integrate analog and digital components for AMS co-simulation.
- Set up and execute parametric simulations and regressions using Cadence Virtuoso ADE-XL.
- Manage functional verification and regression activities using Incisive, vManager and vPlanner.
- Debug simulation failures, model-to-schematic mismatches and analog–digital integration issues.
- Work with simulators such as Spectre, AFS, Incisive and VCS-AMS, and FastSPICE solutions, including CustomSim/FineSimPro.
- Develop automation scripts for simulation setup, regression execution,



results analysis and reporting.
- Optimize CAD flows and simulation performance, and troubleshoot Linux environments and LSF compute infrastructure.
- Collaborate with design, verification, CAD and IT teams to provide Design Engineering support.

Required Skills

- Strong experience in analog/mixed-signal functional and parametric verification.
- Hands-on knowledge of Cadence Virtuoso, ADE-XL and Spectre.
- Experience in AMS modelling using Wreal, SystemVerilog and/or Verilog-AMS.
- Working knowledge of UVM-based testbench methodologies and AMS co-simulation.
- Experience with verification planning, regression execution and simulation debugging.
- Scripting proficiency in one or more of TCL, Shell, Perl, Python or Cadence SKILL.
- Working knowledge of Linux/UNIX, LSF job scheduling and CAD flow troubleshooting.
- Solid analytical, communication and cross-functional collaboration skills.

Additional Relevant Experience

- Cadence Xcelium/Incisive, vManager, vPlanner and UNL.
- AFS, VCS-AMS, CustomSim or FineSimPro.
- Simulation infrastructure support and CAD methodology development.

Qualification B.E./B.Tech or M.E./M.Tech in Electronics, Electrical Engineering, VLSI or a related discipline.

Pay: ₹4,500,000.00 - ₹5,000,000.00 per year

Work Location: In person

📌 Senior AMS Verification Engineer Analog & Mixed Signal (Bengaluru)
🏢 TheKnowledgeHive
📍 Bengaluru

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