- Placement and optimization
- Clock Tree Synthesis (CTS)
- Routing and route optimization
- Static Timing Analysis (STA) and timing closure
- Signal integrity analysis (crosstalk, noise, EM/IR)
- Physical verification (DRC, LVS, ERC)
- Low power implementation (UPF/CPF)
- ECO implementation and signoff
- Collaboration with RTL, DFT, verification, and package teams
- Tapeout readiness and support