We are looking for an experienced Memory Layout Engineer with a minimum of 3+ years of hands-on experience in Memory Layout Design and Physical Layout implementation. The candidate should have exposure to advanced semiconductor technology nodes, particularly TSMC and/or Samsung process technologies.

Key Responsibilities

- Develop and implement memory layout designs based on design specifications.

- Work on memory layout implementation, optimization, and physical verification.

- Ensure layout quality, design accuracy, and compliance with foundry requirements.

- Collaborate with circuit design, physical design, and verification teams.

- Perform layout-related checks and resolve Design Rule Check (DRC) violations.





- Support layout optimization for advanced technology nodes.

Required Skills & Technical Expertise

- Minimum 3+ years of experience in Memory Layout Design.

- Hands-on experience with advanced semiconductor technology nodes.

- Experience with TSMC and/or Samsung process technologies.

- Understanding of memory layout implementation and physical verification.

- Knowledge of DRC, LVS, and other physical verification concepts is preferred.

Technology Node Requirements

TSMC

- A14n

- 2nm

- 3nm

- 5nm

Samsung

- 2nm

- 4nm

📌 Memory Layout Engineer (Bengaluru)
🏢 Dignifyd
📍 Bengaluru