05 Nov
|
Cadence System Design and Analysis
|
New Delhi
05 Nov
Cadence System Design and Analysis
New Delhi
. Proficient in Verilog coding and RTL design, data path designs,
- Knowledge of RTL checks ex- LINT, SDC, CDC
- Familiar with synthesis flow and timing constraints
- Experience in writing Verilog testbench and running simulations.
- Familiar with any of the interface Protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display
📌 Lead RTL Design Engineer (New Delhi)
🏢 Cadence System Design and Analysis
📍 New Delhi