# 1. Analog Design Engineer

Key Responsibilities

- Design, simulate and characterize high-performance and high-speed circuits (e.g. Transmitter, Receiver, LDO, PLL, DLL, LDO).
- Layout supervision, Post-Layout Simulations, Circuit Specification closure
- Circuit Validation (Electrical, functional, Reliability)
- Collateral Generation
- Post silicon validation, and debug

Minimum Qualifications

- Masters with 4 to 10 years of experience in mixed-signal circuit design of analog IPs
- Prior experience designing of analog blocks such as Transmitter, Receiver, PLL, LDO, DLL etc
- Good knowledge of design principles for practical design tradeoffs.
- Desirable experience in Post-Silicon Debug, and Analog methodology
- Experience in modeling (Verilog-A, Verilog) and scripting is desirable.
- The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams.

# 2. Analog Layout Engineer UCIe PHY

Experience: 5+ Years

Location: Bengaluru

Job Summary:

We are looking for an experienced Analog Layout Engineer to work on high-speed UCIe PHY analog/mixed-signal blocks in advanced semiconductor technologies.

Key Responsibilities:

- Develop full-custom analog/mixed-signal layouts for UCIe PHY blocks.
- Layout of TX/RX, PLL/DLL, drivers, receivers, bias/reference and high-speed I/O circuits.
- Perform floorplanning, placement, routing, matching, shielding and noise isolation.
- Handle DRC, LVS, ERC, PEX and layout debug.
- Work closely with circuit designers on parasitic extraction and post-layout optimization.
- Implement advanced-node layout techniques and ensure EM/IR and reliability requirements.
- Participate in layout reviews and deliver blocks from layout through signoff.

Required Skills:





- 5+ years of experience in Analog/Custom IC Layout.
- Good knowledge of analog layout, matching, parasitics, shielding and high-speed routing.
- Experience in advanced CMOS/FinFET technologies.
- Strong DRC/LVS/PEX experience.
- Experience in SerDes / PCIe / USB / DDR / Ethernet / UCIe PHY is preferred.

Ideal Candidate

- A hands-on Analog Layout qualified who can independently own complex blocks such as TX/RX, DDR, UCIe, SERDES, PLL, LDO, Current Mirrors and Differential Pairs from floorplanning to signoff/tapeout.

3. AMS Verification & Validation Engineer

Domain: Analog / Mixed-Signal Design Verification Key Focus: SERDES, High-Speed Interface Circuits, RX/TX Verification

Key Responsibilities

- Develop and execute AMS verification plans, testbenches, and test scenarios for high-speed analog/mixed-signal circuits.
- Perform functional verification of CDR, CTLE, DFE, SERDES TX/RX, and TX voltage/current drivers.
- Develop behavioral models using SystemVerilog Real Number Modeling (SV-RNM/WREAL) and Verilog-AMS.
- Perform mixed-signal simulations, debug failures, and analyze circuit-level and system-level performance.
- Apply UVM-AMS and mixed-signal verification methodologies to improve verification coverage and efficiency.
- Automate test execution, data analysis, and regression workflows using Python and MATLAB.
- Collaborate with analog, digital design, and system teams to identify issues and ensure design quality.

Required Skills & Tools

- Languages & Modeling: SystemVerilog, SV-RNM/WREAL, Verilog-AMS, Python, MATLAB.
- Circuit Expertise: CDR, CTLE, DFE, SERDES TX/RX, TX voltage and current drivers.
- EDA Tools: Cadence Xcelium/Incisive, Cadence Spectre, and Synopsys simulation tools.
- Verification Methodologies: UVM-AMS, mixed-signal simulation, behavioral modeling, testbench development, and debug.

📌 Analog Design, Analog Layout, AMS Verification - Sr. Engineer/ Lead (Bengaluru)
🏢 NEWSOFT CONSULTANTS
📍 Bengaluru