Job highlights
Job type: Full time.
Experience: 4 12 years.

Job Summary

Prove the RTL is right UVM testbenches, coverage and formal before it reaches silicon.

Job Details
Job type: Full time
Experience: 4 12 years
Location: Bengaluru, India

Responsibilities
Build UVM testbenches and constrained-random settings for blocks and SoCs.
Define verification and coverage plans; close functional and code coverage.
Apply formal where it pays, and hunt the escapes simulation nearly misses.

Skills
UVM
SystemVerilog
Coverage
Formal
Assertions
Verification

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📌 Design Verification Engineer Bengaluru (India)
🏢 FASTSTREAM TECHNOLOGIES
📍 India