We are seeking a highly skilled and experienced Senior Design Verification Engineer to join our dynamic team. The ideal candidate will possess a strong background in SOC and IP verification, with expertise in Verilog, System Verilog, and UVM. You will play a critical role in ensuring the quality and reliability of our designs through rigorous verification processes.
Key Responsibilities
- Develop and execute comprehensive verification plans for SOC and IP designs.
- Utilize Verilog and System Verilog to create and maintain testbenches and verification environments.
- Implement UVM-based verification methodologies to enhance the efficiency and effectiveness of the verification process.
- Collaborate with design engineers to understand specifications and requirements for various protocols, including AXI, APB, CHI, and USB.
- Write and maintain verification code in C/C++ to support advanced verification tasks.
- Analyze and debug complex design issues,
providing timely feedback to the design team.
- Mentor junior engineers and contribute to the continuous improvement of verification processes and methodologies.
Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Proven experience in SOC and IP verification, with a robust understanding of digital design principles.
- Proficiency in Verilog, System Verilog, and UVM.
- Solid programming skills in C/C++.
- Familiarity with industry-standard protocols such as AXI, APB, CHI, and USB.
- Strong analytical and problem-solving skills, with a keen attention to detail.
- Excellent communication and teamwork abilities.
Join us in shaping the future of technology by ensuring the highest standards of design verification. If you are passionate about innovation and excellence, we would love to hear from you!