We are seeking an experienced RTL Verification Engineer with expertise in functional verification of complex digital designs using System Verilog and UVM methodologies. The candidate will be responsible for developing verification environments, executing comprehensive verification plans, and ensuring high-quality product delivery.
Key Responsibilities
- Understand design specifications and develop verification strategies and plans.
- Develop UVM/System Verilog-based verification environments.
- Create testcases, scoreboards, monitors, assertions, and coverage models.
- Perform block-level, subsystem-level, and SoC-level verification.
- Drive functional, code, assertion, and toggle coverage closure.
- Execute regressions and analyze simulation results.
- Debug RTL and verification setting issues in collaboration with design teams.
- Participate in reviews and verification sign-off activities.
Role: Hardware and Networks - Other, Industry Type: Miscellaneous, Department: Engineering - Hardware & Networks, Employment Type: Full Time, Permanent Role Category: Hardware and Networks - Other Education UG: B.Tech / B.E. in Any Specialization PG: M.Tech in Any Specialization read more
Key Skills Skills highlighted with ‘‘ are preferred keyskills RTLVerificationSystem Verilog UVMSVAAssertionsRTL DebuggingRegression TestingSoC