We are hiring for one of our top leading semiconductor client. If you're interested and your experience matches the requirement, we'd love to hear from you.
Position: RTL Design Engineer
Experience: 10+ Years
Location: Bengaluru
Contract tenure: 1 year
Top 3 mandatory (primary) skills:
- Verilog, system verilog, UVM
- IP level TB component development
- Mastery in EDA tools (Verdi,vcs) etc
Positive to have (secondary) skills:
- Comfortable in scripting for automation
- AI tools usage
- Experience in digital+analog verification
- Owns IP and top-level ASIC verification for complex SerDes subsystems.
- Domain: Verifies digital RTL integrated with analog behavioral models using SystemVerilog/UVM.
- Alignment: Ensures seamless functionality across digital, analog, and firmware boundaries.
- Metrics:
Drives testbench architecture and test planning to achieve coverage closure.
Job Responsibilities / Day-to-Day Activities
- Spec Review: Analyze design specs and collaborate with designers to align test plans.
- Testbench Development: Build or upgrade UVM testbenches, write tests, and close coverage.
- Cross-Team Integration: Work with RTL, analog, and firmware teams to bridge design gaps and verify system-level interfaces.
- Behavioral Model Verification: Validate subsystem functionality including analog model and firmware interactions in the digital testbench.
- Productivity: Leverage approved automation and AI tools to accelerate debugging and triage.