Requirement Details

- Role: STA / Synthesis Engineer

- Location: Hyderabad

- Experience: 4+ Years (5+ preferred; strong 4-year candidates can be considered)

- Interview Mode: Face-to-Face (Candidates can attend from Bangalore office if required)

Key Skill Requirements

Primary Skills (Mandatory):

1. Synthesis

2. Timing Constraints (SDC)

3. STA / PrimeTime

Secondary Skills (Positive to Have):

- CDC (Clock Domain Crossing)

- RDC (Reset Domain Crossing)

- Lint

- SPG DFT / DFT Sign-off Activities

Role Overview

- Candidate will support the IP team and work on multiple RTL releases.

- Responsible for running synthesis and validating timing constraints.

- Review timing reports and update constraints independently.

- Perform quality sign-off from the IP perspective before handing off to SOC teams.

- Support SOC teams in resolving IP-related timing and constraint issues.

- No ownership of SOC timing closure, congestion closure, or power analysis is required.





Candidate Background The hiring manager is open to candidates from:

- STA Background

- Synthesis Background

- RTL Design Background

- Physical Design (PD) Background

However, candidates must have:

- Hands-on experience with synthesis.

- Strong understanding of timing constraints.

- Ability to analyze timing reports and update constraints independently.

- Experience with PrimeTime is highly preferred.

Additional Notes

- The team is working on Clock IPs with aggressive timing constraints.

- CDC, RDC, Lint, and SPG DFT skills can be learned on the job; these are not strict screening criteria.

- Candidates from Bangalore who are willing to relocate to Hyderabad can be considered.

- Please avoid resubmitting profiles that have already been reviewed/rejected.

📌 Design Engineer with Synthesis ,Primetime/STA (Hyderabad)
🏢 Sunrise BizTech Systems
📍 Hyderabad