At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Verification Infrastructure: Simulation testbenches in C/C++/RTL and lead the development of reusable UVM environments.
Champion the integration of formal verification, and AI-driven coverage analysis.
Partner with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements.
B.Tech/M.Tech in ECE with
Experience in SystemVerilog/UVM and C/C++ for architectural modeling.
Experience with processor integration (e.g., Expertise in scripting (Perl, Python, or Tcl) for verification flow automation.
Proven track record in verifying complex pipelines, memory subsystems, or ISA implementations.
Help us solve what others can't.