Physical Design Engineer (PD Engineer) VLSI / ASIC

Location: Bangalore, Karnataka, India
Work Mode: Onsite Work From Office
Employment Type: Full-Time
Experience: 0 1+ Years (Freshers with relevant practical training may apply)
Qualification: B.E. / B.Tech / M.E. / M.Tech
Minimum CGPA: 8.0 or Above

1. Role Overview

We are looking for a Physical Design Engineer with valuable technical knowledge and practical understanding of ASIC/VLSI Physical Design methodologies.

The role involves Synthesis, Place and Route (P&R;), Static Timing Analysis (STA), and Physical Design implementation from Netlist to GDS-II.

Candidates should understand the key stages of the Physical Design flow, including Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, Timing Closure, and Signoff.

Fresh graduates with relevant VLSI Physical Design training, academic projects, or internship experience may be considered.

2. Key Responsibilities

- Support ASIC Physical Design implementation from Netlist to GDS-II.

- Perform and understand RTL Synthesis and Physical Synthesis methodologies.

- Work on Floorplanning, Macro Placement, and Standard Cell Placement.

- Support Clock Tree Synthesis (CTS) and Clock Optimization.

- Execute Placement and Routing (P&R;) activities.

- Perform Static Timing Analysis (STA) and identify timing violations.

- Assist in Setup and Hold Timing Analysis and Timing Closure.

- Support Timing Optimization and Engineering Change Orders (ECO).

- Understand Physical Verification (PV), including DRC and LVS checks.

- Gain practical exposure to Electromigration and IR Drop (EMIR) analysis and Low-Power Signoff (VCLP).

- Develop and maintain Tcl scripts for Physical Design automation and flow improvements.





- Collaborate with RTL Design, Synthesis, DFT, and Verification teams to support implementation and signoff activities.

3. Required Qualifications
- B.E. / B.Tech / M.E. / M.Tech in Electronics, Electrical, Electronics & Communication, or Computer Engineering.

- Minimum academic CGPA of 8.0 or above.

- 0 1+ years of relevant experience in ASIC/VLSI Physical Design.

- Good understanding of the complete ASIC Physical Design flow.

- Practical knowledge of Synthesis, Place and Route, and Static Timing Analysis.

- Familiarity with Floorplanning, Placement, CTS, Routing, and Timing Closure.

- Understanding of Netlist-to-GDS-II implementation methodologies.

- Relevant hands-on experience through internships, academic projects, industry training, or professional assignments.

- Willingness to work onsite in Bangalore.

- Willingness to commit to the organization for a minimum period of 5 years.

4. Technical Skills

ASIC / VLSI Physical Design

- ASIC Physical Design Flow

- Netlist to GDS-II

- Floorplanning and Placement

- Clock Tree Synthesis (CTS)

- Routing and Physical Optimization

Synthesis and Timing Analysis

- RTL Synthesis

- Physical Synthesis

- Static Timing Analysis (STA)

- Setup and Hold Timing Analysis

- Timing Closure and Timing Optimization

- Engineering Change Orders (ECO)

EDA Tools

- Synopsys Fusion Compiler

- Cadence Innovus

- Familiarity with Physical Design and STA tools

Physical Verification and Signoff

- Design Rule Check (DRC)

- Layout Versus Schematic (LVS)

- Electromigration and IR Drop (EMIR)

- Voltage-Aware Low-Power Signoff (VCLP)

Scripting and Automation

- Tcl Scripting

- Basic knowledge of Perl or Python

- Physical Design Flow Automation

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📌 Physical Design Engineer (PD Engineer) – VLSI / ASIC (Bengaluru)
🏢 Best NanoTech
📍 Bengaluru