We are seeking a highly motivated Memory Layout Engineer with strong expertise in custom layout development for advanced memory compilers. The ideal candidate will have hands-on experience in SRAM/MRAM layout design, physical verification, and close collaboration with circuit design teams to deliver high-quality layouts for advanced technology nodes.

Key Responsibilities
• Design and develop custom layouts for memory macros, including SRAM, MRAM, and other embedded memory architectures.
• Create and optimize hierarchical layouts for memory sub-blocks such as row decoders, write drivers, sense amplifiers, assist circuits, and memory control logic.
• Collaborate closely with circuit designers to ensure layout implementation meets performance, area, power, reliability, and manufacturability requirements.
• Perform and resolve physical verification checks including DRC, LVS, ERC, and reliability-related violations.
• Analyze and mitigate layout-dependent effects, parasitics, and other second-order effects impacting circuit performance.
• Drive layout quality, productivity improvements, and best practices across memory design projects.
• Support project execution across distributed teams and customer engagements. Required Skills & Experience
• Strong understanding of VLSI fundamentals, including CMOS devices, IC fabrication processes, FinFET technology, and RC network concepts.




• Hands-on experience in custom memory layout development for SRAM, MRAM, or similar memory architectures.
• Proficiency with industry-standard EDA tools such as Cadence Virtuoso, Synopsys Custom Compiler, Calibre, ICV, or equivalent.
• Good understanding of layout optimization techniques involving speed, area, power, parasitics, matching, electromigration, and reliability considerations.
• Experience working closely with design teams to achieve design specifications and signoff requirements.
• Solid debugging, problem-solving, and analytical skills.
• Excellent verbal and written communication skills. Preferred Qualifications
• Experience with advanced process technologies and high-density memory designs.
• Ability to independently drive complex layout tasks from concept to tape-out.
• Experience mentoring junior engineers and leading small technical teams.
• Strong documentation, presentation, and stakeholder management skills. Requirements Education BE/B.
Tech in ECE/EEE or M.
Tech VLSI Experience 3
- 5 Years Work Environment
• Flexibility to work from client locations and Offshore Development Centers (ODC) as required.
• Comfortable working with global cross-functional teams across multiple time zones.
• Self-driven professional capable of taking ownership and delivering results in a fast-paced environment. Benefits As per SignOff Policy

📌 Design Engineer II – Memory Layout (Bengaluru)
🏢 SIGNOFF SEMICONDUCTORS
📍 Bengaluru