Experience:
6+ years only 1) Write SV RTL for custom logic at the test chip top (clock, reset, FSM etc.) 2) Experience in lint, cdc, rdc, UPF/LP lint checks Positive to have
skills:
3) Understand requirements and create high level design document and low level micro-architecture for a test chip 4) Test chip integration (hard ip, pads, custom logic, clock, reset etc.) 5) Understanding of UPF 6) Understanding of JTAG/IJTAG interface 7) Basic understanding of DAC IP (DAC IP will be hard macro)
📌 Field-Programmable Gate Arrays Engineer (India)
🏢 HCLTech
📍 India
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