Key Responsibilities:

•Perform characterization of standard cell libraries and hard IPs.

•Generate and validate front-end and back-end design kit views.

•Run transistor-level simulations using SPICE, HSPICE or Spectre.

•Work on standard cell timing, power and performance analysis.

•Perform Monte Carlo simulations and high-sigma analysis.

•Work with tools such as Cadence Liberate, PrimeSim DR, HSA and Solido.

•Develop and automate characterization flows using Python, TCL or Perl.

•Collaborate with Physical Design, RTL and CAD teams to resolve design kit issues.

•Support design kit validation, quality checks and test chip tapeouts.

Required Skills:

•6+ years of experience in VLSI / Semiconductor Engineering.

•Hands-on experience in standard cell or IP characterization.





•Solid knowledge of SPICE simulations and CMOS fundamentals.

•Experience with Cadence Virtuoso, HSPICE or Spectre.

•Familiarity with Liberate, PrimeSim, Totem or similar characterization tools.

•Knowledge of PVT analysis, Monte Carlo simulations and Liberty file generation.

•Positive scripting skills in Python, TCL, Perl or SKILL.

•Understanding of physical verification, DRC, LVS and design kit development.

Valuable to Have:

•Experience with foundry technology and advanced process nodes.

•High-sigma analysis using PrimeSim DR / HSA.

•Experience in test chip design and tapeout.

📌 Senior Vlsi Library Characterization Engineer Bangalore Metropolitan Area (India)
🏢 Sintegra
📍 India