Key Responsibilities
Own DFT insertion, implementation, scan synthesis, verification, and ATPG activities at block and SoC levels.
Implement and validate scan compression, scan chains, MBIST, IJTAG/TAP, OCC, and other DFT structures.
Generate, validate, and optimize stuck-at and transition-delay ATPG patterns for test coverage and test time.
Work on Siemens Tessent SSN, hierarchical ATPG, and pattern retargeting.
Execute and debug RTL, zero-delay, unit-delay, and SDF gate-level simulations.
Perform DFT DRC, quality checks, and debug DFT implementation and timing issues.
Support silicon bring-up, ATE pattern validation, failure analysis, and debug.
Develop automation and scalable DFT methodologies to improve quality and execution efficiency.
Collaborate with Design, Verification, Physical Design, CAD, and Silicon Test teams.

Required Skills
6+ years of hands-on experience in DFT implementation, verification, or ATPG.
Solid knowledge of scan insertion, scan synthesis,



scan compression, ATPG, and DFT clocking.
Hands-on experience with Siemens Tessent DFT tools and hierarchical DFT methodologies.
Experience with Verilog/SystemVerilog, VCS, and gate-level simulations (GLS/SDF).
Solid debugging, analytical, and problem-solving skills.
Proficiency in Tcl, Python, or Shell scripting.

Preferred Skills
Experience with Tessent SSN, hierarchical pattern retargeting, and test time optimization.
Knowledge of MBIST, IJTAG, OCC, and at-speed testing.
Experience with STIL/WGL, ATE testing, and post-silicon debug.
Exposure to multi-die/chiplet-based SoC architectures.

What We Look For

A hands-on engineer with solid technical ownership, excellent debugging skills, and the ability to independently drive complex DFT activities from RTL through silicon bring-up.

📌 Dft Engineer Bengaluru
🏢 Hays
📍 Bengaluru