Job Summary

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Senior/Lead Design Verification Engineer to join our Memory Controller IP team in Bangalore, India. The successful candidate will participate in pre-silicon RTL Verification activities related to Memory Controller SoftIP development, on leading-edge DDR, HBM, GDDR, and LPDDR DRAM controller technologies. This is a Full Time position, reporting to a local onsite manager of India Memory Controller Verification.

Responsibilities

- Testbench and test sequence development for verification of new controller technologies and features
- Functional coverage planning, coverage item coding, and test suite augmentation to achieve Functional Coverage
- Regression test development, monitoring, debug/triage, and correction to test environment, sequences, debug of controller RTL design




- Development & support of Verification environment scripting and capabilities

Qualifications

- Bachelors Degree or above in EE/CS, minimum 8+ years experience with HDL logic Design-Verification
- System Verilog testbench, Verilog/System Verilog logic design/RTL fluency a must
- Pre-existing Experience / familiarity with DDR DRAM technology a robust preference
- Working experience with Python and TCL scripting languages preferred

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Lead MTS Verification Engineering (Bengaluru)
🏢 Rambus Chip Technologies
📍 Bengaluru