Job Summary

Very positive understanding of timing concepts

Responsibilities

- Work with the design and implementation teams to develop and qualify timing constraints

- Work closely with the physical design engineers to resolve implementation related timing issues

- Should be able to plan and track self execution and report result on regular basis systematically

- Should be able to solve timing challenges in Block/SOC by manually closing difficult paths

Requirements

- Should have understanding of SDC and constraints syntax

- Experience in Timing Analysis both at block level and SoC level

- Experience with Industry Timing signoff tools like Primetime / Tempus is a must

- Experience in DMSA or Tweaker

- Should have understanding of different Timing modes and Corners

- Experience in MMMC

- Should have worked on Timing ECO generation in multi-voltage designs

- Experience Timing & Noise Signoff Closure at block level or Full chip-level on advanced process nodes

📌 STA (STATIC TIMING ANALYSIS) ENGINEERS | VLSI (Noida)
🏢 Shashwath Solution
📍 Noida