Job highlights

- Familiarity with VCS / Xcelium and Verdi . Good debugging and analytical skills
- Required Skills
- Preferred Skills
- 4-6 years RTL Design experience . Solid Verilog / System Verilog coding . Digital Design fundamentals . FSM .

Position: RTL Design Engineer (BB46FT RM 4562) Role Summary The RTL Design Engineer will independently develop synthesizable RTL for assigned blocks under the guidance of the Technical Lead while collaborating with verification and implementation teams.

Responsibilities

- Develop synthesizable Verilog/System Verilog RTL.
- Understand design specifications and implement block-level functionality.
- Perform RTL simulations and debug failures.
- Resolve o Lint issues o CDC violations o RDC violations
- Support synthesis and timing closure activities.
- Participate in design reviews.
- Prepare RTL documentation.
- Work closely with DV, STA and PD engineers.

Required Skills

- 4-6 years RTL Design experience
- Strong Verilog/System Verilog coding




- Digital Design fundamentals
- FSM
- Counters
- FIFOs
- Arbitration logic
- State Machines
- Pipeline design
- Reset handling
- Clock gating
- CDC basics
- RDC basics
- Lint analysis
- Simulation debugging
- Synthesis awareness
- Familiarity with VCS/Xcelium and Verdi
- Good debugging and analytical skills

Preferred Skills

- AXI/AHB/APB
- UPF basics
- Git/Perforce
- Python/TCL scripting
- FPGA exposure (optional)

Job Category: Embedded HW_SW

Job Type: Full Time

Job Location: Bangalore

Experience: 4-6 years

Notice period: 0-30 days

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 RTL Design Engineer (Bengaluru)
🏢 Sourceright Technologies
📍 Bengaluru