# 1. RTL Design Engineer (6 to 12 Years)

Location: Hyderabad/ Bangalore

- Develop RTL designs using Verilog/SystemVerilog based on architecture specifications.
- Define and implement digital micro-architecture for SoC/IP blocks.
- Design and integrate modules related to:
- Motor Control Systems
- Industrial Communication Interfaces
- Embedded Controllers
- DMA, Interrupt Controllers
- GPIO, Timers, PWM Modules
- UART, SPI, I2C, CAN, Ethernet Interfaces
- Perform RTL coding, linting, CDC and quality checks.
- Analyze architecture specifications and convert them into RTL implementation.
- Support functional verification teams during simulation and debug activities.
- Collaborate with DFT teams for scan insertion and testability requirements.
- Work with Synthesis and Physical Design teams to close implementation issues.
- Participate in RTL reviews, design reviews, and code reviews.
- Prepare RTL documentation and design specifications.

# 2. STA - Sr Engineer / Lead (5 to 12 Years)

Location: Hyderabad/ Bangalore

Static Timing Analysis & Signoff

- Perform block-level and full-chip timing analysis and signoff.
- Drive timing closure across all functional and test modes.
- Analyze and fix setup, hold, recovery, removal, transition, capacitance, and pulse-width violations.
- Perform timing signoff across multiple process, voltage, and temperature corners.
- Execute MCMM (Multi-Corner Multi-Mode) timing analysis and closure.
- Validate timing across hierarchical and flat SoC designs.

Timing Closure

- Drive setup and hold optimization throughout implementation cycles.
- Work closely with Physical Design teams to achieve timing convergence.




- Perform timing ECO generation and validation.
- Analyze critical timing paths and propose optimization strategies.
- Resolve timing bottlenecks while maintaining area and power targets.
- Support late-stage tapeout closure activities.

Signal Integrity & Noise Analysis

- Perform Crosstalk Analysis.
- Analyze and resolve SI-related timing issues.
- Validate noise, glitches, and signal integrity effects.
- Work closely with physical design teams on route optimization and shielding techniques.
- Ensure timing robustness under SI effects.

Low Power Verification

- Verify clock gating implementations.
- Analyze UPF/CPF constraints.
- Validate low-power modes and timing requirements.
- Support power-aware timing signoff methodology.

# 3. DFT Lead (10 to 20 Years)

Location: Hyderabad/ Bangalore

Exp Range:

DFT Architecture & Planning

- Define and develop DFT strategy for complex ASIC and SoC designs.
- Create DFT specifications and test architecture documents.
- Drive DFT implementation activities from RTL through tapeout.
- Collaborate with RTL, Design Verification, Physical Design, STA, and Silicon Validation teams.
- Ensure high fault coverage while meeting PPA requirements.
- Participate in architecture reviews and DFT signoff activities.

Scan Insertion & Test Compression

- Design and implement scan architecture.
- Perform scan chain insertion and optimization.
- Implement scan compression methodologies.
- Analyze and debug scan chain violations.
- Support scan-chain reordering and physical-aware DFT implementation.
- Optimize test time and tester memory utilization.

📌 Hiring | STA, DFT & RTL Design - Tech Lead/ Sr. Engineer's (Bengaluru)
🏢 NEWSOFT CONSULTANTS
📍 Bengaluru