With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

Drive full-chip or subsystem static timing analysis and timing closure across multiple modes and corners. The role needs strong constraint understanding, path-level debugging, timing-model awareness and the ability to translate analysis into implementable ECO actions.

Debug interface timing, block-to-block paths, clock interactions and constraint-quality issues

Build, validate and use timing models for hierarchical analysis where applicable

Generate timing ECO recommendations and work with PnR/implementation teams through closure

5-10 years of relevant STA/timing closure experience at subsystem or full-chip level

Solid SDC knowledge and experience debugging incorrect, incomplete or conflicting constraints





Experience with MCMM timing analysis, path-based debugging and timing ECO generation

Exposure to implementation tools such as Innovus, ICC2 or Fusion Compiler for timing correlation

Ability to communicate timing risks and closure actions clearly to implementation and design teams

Python is an advantage

Has the candidate owned STA closure at subsystem or full-chip level, not only generated timing reports

Which PrimeTime/Tempus analyses were used hands-on, including SI and variation methodology where applicable

BE/BTech/MTech in Electronics, Electrical Engineering or a related discipline.

We believe that our company culture is the key to our ability to make a true difference in every industry we reach. We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas.

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