Lead Design Verification Engineer

Location: Bengaluru

Experience: 6–12 Years

Role Overview

We are looking for a technically strong Lead Design Verification Engineer with extensive hands-on experience in IP/SoC verification, SystemVerilog, UVM and PCIe protocols (Gen5/Gen6/Gen7). The ideal candidate should have robust expertise in developing scalable verification environments, building robust testbenches and driving complex protocol-level verification from specification to signoff.

Key Responsibilities:
Lead hands-on design verification of complex PCIe IP/SoC blocks across Gen5, Gen6 and Gen7.
Develop and maintain reusable, scalable UVM-based verification environments.
Architect and implement SystemVerilog-based testbenches, agents, sequences, drivers, monitors and scoreboards.
Develop constrained-random, directed and coverage-driven verification strategies.
Verify PCIe protocol features, transaction handling, link training, configuration, power management and error handling.
Drive functional coverage, code coverage and verification closure.
Debug complex RTL and simulation failures through waveform analysis and root-cause investigation.
Collaborate closely with RTL,



Architecture and System teams to resolve design and verification issues.
Drive verification planning, execution, regression management and signoff.

Mandatory Technical Skills:
6–12 years of hands-on experience in ASIC/SoC Design Verification.
Solid expertise in SystemVerilog and UVM.
Extensive experience in developing and debugging complex UVM testbenches.
Strong hands-on verification experience in PCIe Gen5 / Gen6 / Gen7.
Good understanding of PCIe protocol architecture, transaction and data link layers, LTSSM and link training.
Expertise in constrained-random verification, assertions (SVA), functional coverage and coverage closure.
Solid debugging skills with simulation and waveform analysis tools.
Proficiency in scripting languages such as Python, Perl or Tcl.

Preferred Skills:
Experience in PCIe Controller, PHY or Subsystem verification.
Exposure to PCIe compliance, protocol corner cases and error injection.
Knowledge of AXI, CXL, NVMe or other high-speed interface protocols.
Experience with Synopsys VCS, Cadence Xcelium or Siemens Questa.

📌 Lead Design Verification Engineer Bengaluru
🏢 leadsoc technologies
📍 Bengaluru