Staff Engineer – Design for Testability (DFT)

Location: Bengaluru, India

Experience: 7–12 Years

Role Overview

We are looking for a technically strong Staff Engineer – DFT with extensive hands-on experience in MBIST, ATPG and Scan Insertion for complex ASIC/SoC designs. The ideal candidate should have solid expertise in end-to-end DFT implementation, test architecture, coverage optimization and production test readiness.

Key Responsibilities
Drive end-to-end DFT implementation for complex IP and SoC designs.
Develop and implement scan insertion strategies, including scan chain architecture, stitching and optimization.
Own MBIST architecture, memory test implementation and test coverage closure.
Develop and optimize ATPG patterns for stuck-at, transition delay and other fault models.
Drive DFT rule checking (DRC), test coverage analysis and pattern validation.
Perform scan compression, test point insertion and pattern optimization.
Debug DFT-related issues and resolve coverage, timing and testability challenges.
Collaborate with RTL, Physical Design, STA and Silicon Validation teams for DFT integration and signoff.
Support post-silicon bring-up,



manufacturing test and production test readiness.

Mandatory Technical Skills
7–12 years of hands-on experience in ASIC/SoC DFT implementation.
Solid expertise in MBIST, ATPG and Scan Insertion.
Solid understanding of scan architecture, scan compression and test methodologies.
Hands-on experience with stuck-at, transition delay and fault coverage analysis.
Strong knowledge of MBIST controllers, memory test algorithms and repair methodologies.
Experience in DFT DRC, pattern generation, coverage analysis and debugging.
Proficiency in industry-standard DFT tools such as Synopsys TestMAX / TetraMAX, Mentor Tessent or equivalent.
Robust understanding of DFT timing constraints and physical implementation considerations.

Preferred Skills
Experience in hierarchical and full-chip DFT implementation.
Exposure to boundary scan (JTAG), IEEE 1149.1 and IEEE 1500.
Knowledge of Logic BIST (LBIST), OCC and ATPG pattern optimization.
Experience working on advanced-node ASIC/SoC designs.
Understanding of manufacturing test flows and silicon test requirements.

📌 Staff Engineer – Design For Testability Dft Bengaluru
🏢 leadsoc technologies
📍 Bengaluru