We are looking for experienced DFT Engineers to work on next-generation, high-performance SoCs. The role involves DFT implementation, scan synthesis, ATPG, DFT verification, SSN, GLS, and silicon debug activities.

Key Responsibilities
Drive DFT insertion, implementation, scan synthesis, verification, and ATPG at block and SoC levels.
Implement scan compression, scan chains, MBIST, IJTAG/TAP, OCC, and other DFT structures.
Generate and optimize stuck-at and transition-delay ATPG patterns.
Work with Siemens Tessent and hierarchical DFT methodologies.
Perform RTL, zero-delay, unit-delay, and SDF gate-level simulations.
Debug DFT implementation, timing, and DFT DRC issues.
Support silicon bring-up, ATE pattern validation, failure analysis, and post-silicon debug.
Develop automation using Tcl, Python, or Shell.
Collaborate with Design,



Verification, Physical Design, CAD, and Silicon Test teams.

Required Skills
6+ years of hands-on experience in DFT implementation, verification, or ATPG.
Robust experience in Scan Insertion, Scan Compression, Scan Synthesis, ATPG, and DFT Clocking.
Hands-on experience with Siemens Tessent.
Experience with Verilog/SystemVerilog, VCS, and GLS/SDF.
Robust debugging and analytical skills.
Good scripting skills in Tcl/Python/Shell.

Valuable to Have
Tessent SSN
Hierarchical ATPG and Pattern Retargeting
MBIST / IJTAG / OCC
STIL/WGL
ATE Testing
Post-Silicon Debug
Multi-die / Chiplet SoC experience

📌 Senior Dft Engineer Bengaluru (India)
🏢 Exiger Technologies
📍 India