Asic Engineer Design Verification, Uvm, Testbench Bengaluru

Asic Engineer Design Verification, Uvm, Testbench Bengaluru

08 Nov
|
Cisco
|
Bengaluru

08 Nov

Cisco

Bengaluru

Job Summary

Meet The team: Silicon one group delivers the silicon, optics, and

Your Impact

As a Design Verification Engineer specializing in Simulation, you will be responsible for developing and executing verification strategies to ensure the correctness and performance of complex hardware designs. Your primary focus will be on emulation platforms to accelerate verification cycles and improve coverage.

Key Responsibilities
Develop and implement verification plans and test benches using Simulation tools and methodologies.
Collaborate with design and validation teams to identify verification requirements and coverage goals.
Utilize emulation platforms to run large-scale verification tests and debug design issues.
Analyse verification results, identify bugs, and work closely with design engineers to resolve issues.
Maintain and enhance verification infrastructure and automation frameworks.
Document verification processes, test cases,



and results to ensure traceability and reproducibility.
Stay current with emerging verification technologies and best practices, particularly in emulation.
Mentor junior engineers and contribute to team knowledge sharing.

Qualifications
Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 1 year of related experience
Solid experience in Desiverification methodologies using UVM or OVM
Relevant experience in design verification with a solid emphasis Test Methodologies
Experience into Networking (Ethernet , AXI, AMBA, Pcie etc)

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Asic Engineer Design Verification, Uvm, Testbench Bengaluru
🏢 Cisco
📍 Bengaluru

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