Company Description:

MosChip® Technologies is a publicly traded company specializing in Silicon and Product Engineering solutions, with over 1300 engineers across Silicon Valley, USA, and India. The company provides end-to-end silicon design, verification, systems, software, and device engineering, as well as multimedia, mobility, connectivity, AI/ML solution design, and test automation services. MosChip® is also known for its development of Digital IPs, Verification IPs, Mixed Signal IPs, and comprehensive Turnkey ASIC services.

The organization has shipped millions of connectivity ICs and achieved an outstanding record of first-time-right silicon across more than 200 SoC tape-outs. This depth of experience offers engineering professionals a dynamic environment for working on complex, high-impact semiconductor products.

Role Description:

The Senior/Lead DFT Engineer will be responsible for architecting, implementing, and validating design-for-test strategies for complex SoCs and ASICs in collaboration with design, verification, and physical design teams. Day-to-day tasks include developing and integrating DFT architectures (scan, MBIST, LBIST, boundary scan), creating test plans, generating test patterns, analyzing coverage, and optimizing testability and manufacturing yield. The role involves working closely with test engineering teams to bring up devices on automated test equipment, debugging test failures,



and driving continuous improvements in test methodologies and flows.

This is a full-time, on-site role based in the Greater Bengaluru Area, with opportunities to coordinate with teams in Hyderabad and other company locations.

Qualifications:

- Minimum 5 to 12 years of strong expertise in Test Engineering and Testing, including implementation and debugging of DFT features for complex digital ICs.
- Hands-on experience in Test Design and Test Equipment usage for semiconductor devices, including ATE-based production testing.
- Solid foundation in Electrical Engineering principles as applied to digital and mixed-signal IC design and validation.
- Proficiency in DFT techniques such as scan insertion, ATPG, MBIST/LBIST, boundary scan (JTAG), and test coverage analysis.
- Experience with industry-standard EDA tools for DFT (e.g., Synopsys, Cadence, Mentor), and familiarity with scripting languages (e.g., Python, Perl, TCL, Shell) for automation.
- Proven ability to lead technical initiatives, mentor team members, and collaborate effectively with cross-functional engineering teams.
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or related field; prior experience in SoC/ASIC projects is highly desirable.
- Solid analytical, problem-solving, and communication skills, with a commitment to quality, reliability, and on-time delivery.

📌 Senior/Lead DFT (Design for Test) Engineer-Bangalore & Hyderabad (Bengaluru)
🏢 MosChip®
📍 Bengaluru