About the Company

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications.

EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

www.EnchargeAi.com The 10 Hottest Semiconductor Startups Of 2025 (So Far)

https://www.crn.com/news/components-peripherals/2025/the-10-hottest-semiconductor-startups-of-2025-so-far?page=11

https://www.enchargeai.com/blog/the-efficiency-imperative-energy-will-define-ais-next-chapter

About the Role

Principal Physical Design Engineer (RTL-to-GDSII) Bangalore EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. You are responsible for transforming raw RTL into world-class silicon by eliminating systemic bottlenecks and building a scalable, predictable path to GDSII. In this role, you aren't just a "user" of tools; you are an engineer who shapes how silicon is built.

You will have the autonomy to overhaul legacy flows and the resources to execute on cutting-edge nodes that define the industry's future.

Job Title: Principal Physical Design Engineer (RTL-to-GDSII)

- Experience: 14-20 Years
- Technology Focus: Sub-5nm (3nm/2nm)
- Location: Bangalore ( Hybrid- 2days office, 3 days-home) Location:



Bangalore Hybrid

The Vision We are seeking a Principal Physical Design Engineer who thrives on complexity and rejects the "black box" approach to EDA tools. This role is for a First Principles thinker who questions the status quo. If a standard flow isn't yielding the desired PPA (Power, Performance, Area), you dive into the PDK, the tool algorithms, and the methodology to find a better way.

Responsibilities

- Full-Flow Ownership: Lead the implementation of massive, high-speed blocks/SoCs from Synthesis through Sign-off using the Cadence Digital Suite.
- PPA Optimization: Push the theoretical limits of the PDK and tools. You will analyze and optimize the interplay between library cells, metal stacks, and tool engines to squeeze out every millivolt and picosecond.
- Methodology & Scalability: Build and refine a "Push-Button" style execution methodology that is robust, repeatable, and minimizes manual "human-in-the-loop" iterations.
- Cross-Functional "Left-Shift": Collaborate with RTL, Architecture, and DFT teams to influence design decisions early. You will drive a holistic approach where physical constraints inform the architecture, not just react to it.
- Bottleneck Elimination: Identify "drag" in the execution pipeline—whether it’s runtime,



convergence issues, or tool limitations—and architect automated solutions to bypass them.
- Mentorship: You act as a force multiplier, elevating the technical competence of the entire PD team.

Qualifications

- Experience: 14-20 years in Physical Design with a proven track record of multiple sub-5nm tape-outs.

Required Skills

- Tool Suite Mastery of Cadence Innovus, Tempus, Joules, Pegasus, and Voltus. (cadence software)
- Advanced Nodes Deep understanding of sub-5nm physics: EUV constraints, multi-patterning, FinFET and IR/EM challenges.
- Sign-off Expert-level knowledge in Static Timing Analysis (STA), Physical Verification (PV), and Power Integrity (PI) and ECO methodology.
- Scripting Proficiency in Tcl and Python to develop custom flow wrappers and data-mining tools for PPA analysis.
- Soft Skills & Leadership Holistic Thinking: You look at the "Big Picture." You solve timing by fixing the floorplan or the RTL/ARCH.
- Influence & Rapport: You can build strong technical bridges with Front-End, Foundry, and EDA vendors to align on a unified execution strategy.
- Critical Thinking: You operate on first principles. You don't just follow a vendor's "Best Practices" if they don't make sense for our specific architecture.

Preferred Skills

- PDK
- Cadence
- Innovus
- tempus
- Genus
- Voltus
- redhawk
- ECO
- PI
- PPA
- Joules
- Pegasus
- PV
- 3nm
- 2nm
- SoC
- Full-chip

Pay range and compensation package

Not specified.

Equal Prospect Statement

Not specified.

Contact

Contact: Uday Mulya Technologies [email protected] www.mulyatech.com

📌 Principal Physical Design Engineer ( Hybrid- 2days office, 3 days-home) (Bengaluru)
🏢 EnCharge AI
📍 Bengaluru