Consultant Job Descriptions

Engagement: Consultant (contract) | Experience: 5–10 years |

Common engagement details: Remote (US-Shift) (7.30 PM to 4.30 AM)

Design Verification Engineer

JD:

Opportunity Overview

Digital functional verification engineers responsible for the planning, strategy, and execution of challenging FPGA verification projects. Work under the technical supervision of a Verification Lead. The position requires interfacing with other functional groups (e.g. Hardware, software, applications).

All About You

We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position.

•Master’s Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science or closely related field with a minimum of 4 years of relevant work experience OR Bachelor’s Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science or closely related field with a minimum of 6 years of relevant work experience

•Experience with Verification Test Plan (e.g. Cadence ePlanner)

•Experience with EDA Tools (e.g. Cadence Xcelium, Simvision)

•Experience with System Verilog Constraint Random Testing,



Assertions and Functional Coverage

•Experience with UVM Testbench Components development and integration

•Experience with UVM Tests sequences development and testing

•Expertise with Verification IP integration

•Experience with System Verilog/UVM based reference models/Predictors development and integration

•Experience with Industry Standard Protocols (e.g. AXI, PCIe, DDR3/4/5)

•Experience working with revision source control (e.g. clearcase, git, svn)

•Detailed oriented with the ability to bring issues to closure.

Desired (but not required) skills/experience:

•Experience in FPGA design implementation with System Verilog

•Experience in verification of Automated Test Equipment functionality

•Experience writing automation scripts (e.g. Make files, shell programming, TCL, Perl, Python)

Pay: ₹60,000.00 - ₹120,000.00 per month

Perks:

- Health insurance
- Provident Fund

Ability to commute/relocate:

- Hyderabad, Telangana 500099: Reliably commute or planning to relocate before starting work (Preferred)

Application Question(s):

- Are you an Immediate joiner?

Experience:

- Design Verification: 5 years (Preferred)

Work Location: In person

📌 Design Verification Engineer (Hyderabad)
🏢 MaximaTek
📍 Hyderabad