Physical Design Lead (ASIC/SoC)

Experience: 12+ Years

Domain: VLSI / Semiconductor / ASIC Design

Job Location: Bengaluru

Employment Type: Full-time

- Job Overview

We are looking for an experienced Physical Design Lead with 12+ years of experience in ASIC/SoC Physical Design implementation and leadership.

The ideal candidate should have strong expertise in end-to-end physical design implementation, from floorplanning and power planning to placement, clock tree synthesis, routing and physical signoff.

The candidate will be responsible for leading physical design activities for complex SoC/ASIC projects, driving timing closure, optimizing power, performance and area (PPA), and ensuring successful implementation and signoff across advanced technology nodes.

The role requires strong technical leadership, hands-on experience with industry-standard EDA tools, and the ability to manage cross-functional teams and drive project execution.

- Key Responsibilities

A. Physical Design Implementation
- Lead end-to-end physical design implementation for complex ASIC/SoC designs.
- Drive the complete physical design flow, including:
- Floorplanning and partitioning.
- Power planning and power grid implementation.
- Placement and optimization.
- Clock Tree Synthesis (CTS).
- Global and detailed routing.
- Post-route optimization.
- Physical verification and signoff.
- Review design specifications and implementation requirements.
- Drive physical design methodologies and ensure adherence to project guidelines.
- Ensure successful implementation of large and complex design blocks and full-chip designs.

B. Timing Closure and Optimization
- Own timing closure activities across pre-route and post-route stages.
- Work closely with STA teams to resolve setup and hold violations.
- Analyze critical timing paths and drive timing optimization strategies.
- Optimize timing through cell sizing, buffering, placement optimization and routing improvements.
- Handle timing constraints, clock uncertainty, latency and skew-related issues.
- Drive multi-mode multi-corner (MMMC) timing closure.
- Collaborate with RTL and synthesis teams to address RTL-level and synthesis-related timing bottlenecks.
- Ensure timing signoff requirements are met across all operating corners.

C. Clock Tree Synthesis and Routing
- Lead clock tree synthesis implementation and optimization.
- Optimize clock skew, insertion delay, latency and clock transition.
- Handle clock distribution challenges in complex SoC designs.




- Drive routing optimization and congestion management.
- Resolve signal integrity and crosstalk-related issues.
- Optimize routing for timing, power and area.
- Handle antenna violations, routing DRCs and connectivity issues.

D. Power, Performance and Area Optimization
- Drive PPA optimization across the physical design flow.
- Analyze and optimize power consumption, performance and silicon area.
- Handle IR drop and electromigration analysis and closure.
- Optimize power distribution networks and power grid implementation.
- Work on dynamic and leakage power optimization.
- Collaborate with design teams to improve overall implementation efficiency.
- Ensure design compliance with power and reliability requirements.

E. Physical Verification and Signoff
- Drive physical design signoff activities.
- Ensure closure of DRC, LVS, antenna and physical verification violations.
- Work on signal integrity and parasitic extraction analysis.
- Drive IR drop and EM signoff.
- Coordinate with STA and physical verification teams for final signoff.
- Ensure all implementation requirements are met before tapeout.

F. Advanced Technology Node Experience
- Drive physical design implementation across advanced technology nodes.
- Work on technology-specific implementation challenges and methodologies.
- Experience with FinFET-based technologies and advanced process nodes.
- Understand technology-dependent challenges related to routing, congestion, power delivery and timing closure.
- Work with foundry-specific design rules and implementation guidelines.

G. Technical Leadership and Team Management
- Lead and mentor a team of physical design engineers.
- Allocate tasks, monitor project progress and ensure timely execution.
- Drive technical reviews, design reviews and implementation signoff.
- Provide technical guidance for complex physical design challenges.
- Collaborate with RTL, STA, DFT, verification and architecture teams.
- Drive methodology improvements and implementation efficiency.
- Identify project risks and develop mitigation strategies.
- Participate in customer interactions, technical discussions and project planning.




- Ensure delivery quality and adherence to project milestones.

3. Required Technical Skills
- 12+ years of experience in ASIC/SoC Physical Design.
- Strong hands-on experience in end-to-end physical design implementation.
- Expertise in floorplanning, placement, CTS, routing and physical signoff.
- Strong experience in timing closure and optimization.
- Hands-on experience with multi-mode multi-corner (MMMC) implementation.
- Solid understanding of STA fundamentals and timing constraints.
- Experience in power planning, IR drop and EM analysis.
- Good understanding of signal integrity, crosstalk and parasitic effects.
- Experience with physical verification, DRC, LVS and antenna checks.
- Experience working on complex SoC designs.
- Strong debugging, problem-solving and technical leadership capabilities.

4. EDA Tools Hands-on experience with one or more of the following:

Physical Design:

- Synopsys ICC2
- Synopsys Fusion Compiler
- Cadence Innovus

Static Timing Analysis:

- Synopsys PrimeTime
- PrimeTime SI

Physical Verification:

- Siemens Calibre
- Synopsys IC Validator

Power Integrity:

- Ansys RedHawk
- Cadence Voltus

Parasitic Extraction:

- StarRC
- Quantus

5. Preferred Skills
- Experience in advanced technology nodes such as 16nm, 7nm, 5nm, 3nm or below.
- Strong exposure to FinFET technology.
- Experience in large-scale SoC and full-chip physical design.
- Knowledge of low-power design methodologies and UPF.
- Experience in hierarchical physical design and block-level integration.
- Exposure to ECO implementation and metal-only ECOs.
- Knowledge of Tcl, Python or Perl scripting.
- Experience in customer-facing technical discussions and project delivery management.
- Experience in leading teams of 5–15+ engineers.

6. Education B.E./B.Tech/M.Tech in Electronics, Electrical Engineering, VLSI or a related discipline.
- Expected Candidate Profile The candidate should demonstrate:

- Strong technical ownership of the complete physical design flow.
- Proven experience in leading physical design implementation for complex ASIC/SoC projects.
- Ability to independently debug and resolve complex timing and physical design challenges.
- Experience in managing and mentoring physical design teams.
- Ability to interact with customers and drive technical discussions.
- Strong understanding of advanced-node implementation challenges.
- Accountability for project execution, quality and tapeout deliverables.

📌 Senior Physical Design Engineer (Bengaluru)
🏢 leadIC Design
📍 Bengaluru