Experience: 6+ Years

Domain: VLSI / Semiconductor

Job Location: Bengaluru / Hyderabad

Employment Type: Full time

Job Overview

We are looking for an experienced Full Chip Static Timing Analysis (STA) Engineer with 6+ years of experience in timing analysis and signoff for complex SoC designs. The ideal candidate should have strong expertise in full-chip STA, timing constraints development, timing closure, and signoff methodologies across advanced technology nodes.

Key Responsibilities

- Perform full-chip Static Timing Analysis (STA) for complex SoC designs.
- Develop, review and validate timing constraints using Synopsys Design Constraints (SDC).
- Perform setup and hold timing analysis across multiple PVT corners and operating modes.
- Analyze and debug timing violations and drive timing closure in collaboration with RTL, synthesis and physical design teams.
- Perform multi-mode multi-corner (MMMC) timing analysis.
- Analyze and resolve timing issues related to clock skew, latency, uncertainty and clock domain crossings.
- Perform timing signoff for functional and test modes.
- Analyze timing paths across hierarchical blocks and full-chip interfaces.
- Work on timing ECOs and coordinate with physical design teams for timing optimization.
- Perform clock-related analysis, including clock tree latency, skew and clock propagation.
- Analyze SI-aware timing, crosstalk and signal integrity impacts on timing.




- Generate and review timing reports and provide recommendations for timing closure.
- Ensure timing signoff quality and adherence to project schedules.

Required Technical Skills
- 6+ years of experience in Static Timing Analysis.
- Strong hands-on experience in Full Chip STA and timing signoff.
- Expertise in SDC constraints development and validation.
- Strong understanding of setup, hold, recovery, removal and pulse-width checks.
- Experience with multi-mode multi-corner (MMMC) timing analysis.
- Hands-on experience with Synopsys PrimeTime.
- Good understanding of clock tree synthesis, clock skew, latency and uncertainty.
- Experience in timing analysis across advanced technology nodes.
- Strong knowledge of STA fundamentals, timing exceptions and false/multicycle paths.
- Experience in debugging timing violations and driving timing closure.
- Proficiency in Tcl scripting; Python or Perl scripting is an added advantage.

Preferred Skills
- Experience with advanced technology nodes (7nm, 5nm, 3nm or below).
- Experience in SI-aware STA and crosstalk analysis.
- Knowledge of AOCV, POCV and OCV methodologies.
- Exposure to IR-drop-aware timing analysis.
- Experience with Synopsys PrimeTime SI.
- Understanding of low-power design methodologies and UPF.
- Experience with large and complex SoC designs.
- Exposure to ECO implementation and timing signoff flows.

Education B.E./B.Tech/M.Tech in Electronics, Electrical Engineering, VLSI or a related discipline.

📌 Full Chip STA Engineer (Bengaluru)
🏢 leadIC Design
📍 Bengaluru