This role involves developing and executing formal verification strategies, writing assertions and cover properties, debugging RTL designs, and fostering cross-team collaboration to uphold rigorous quality standards and functional specifications.

This role is hybrid, based out of Bangalore, IN.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

- 6+ years of Demonstrated experience in applying formal methods to sign off designs or sub-components of designs.
- Detail-oriented with a desire to overcome complex challenges.
- Strong analytical skills to tackle sophisticated problems.
- Possess strong communication and excellent interpersonal skills for effective team collaboration.

What We Need





- Solid background and hands-on experience with formal methods and their application to hardware verification.
- Experience using EDA formal tools such as Jasper, VC-Formal, Questa for property checking and formal regression. - Experience or Trained on FUSA (Functional Safety) concepts for verification.
- Experience with Verilog/SystemVerilog HDLs and ability to understand sophisticated RTL quickly.
- Experience writing assertions, cover properties, and connectivity checks.

What You Will Learn

- Contribute to flow and script development to improve team efficiency.
- Collaborate closely with microarchitecture, DV, and RTL teams to ship robust silicon.

📌 Formal Verification engineer (Bengaluru)
🏢 Tenstorrent
📍 Bengaluru