DFT Engineer (ATPG Pattern Generation)

Experience: 3+ Years

Domain: VLSI / Semiconductor

Job Location: Hyderabad

Employment Type: Full-time

Job Overview

We are looking for a DFT Engineer with 3+ years of experience in Design for Testability (DFT), with robust hands-on expertise in ATPG pattern generation and scan-based testing methodologies.

The ideal candidate should have practical experience in scan insertion, ATPG pattern generation, fault simulation, test coverage analysis and pattern debugging. The candidate will work closely with RTL, Physical Design and Verification teams to ensure testability and improve manufacturing test coverage for complex ASIC/SoC designs.

Key Responsibilities

- Implement DFT methodologies for ASIC/SoC designs.
- Perform scan insertion and scan chain implementation.
- Generate ATPG patterns for stuck-at and transition fault models.
- Perform fault simulation and analyze test coverage.
- Debug ATPG pattern generation issues and improve fault coverage.
- Analyze and resolve DFT DRC violations.
- Work on scan chain connectivity, scan compression and test architecture.
- Perform pattern validation and ATPG coverage analysis.
- Support MBIST and memory test integration, where required.
- Collaborate with RTL, synthesis and physical design teams for DFT implementation.




- Support pattern handoff and test-related activities for production and silicon testing.

Required Technical Skills
- Minimum 2+ years of experience in DFT implementation.
- Mandatory hands-on experience in ATPG pattern generation.
- Strong understanding of scan-based DFT architecture and methodologies.
- Experience in stuck-at and transition fault ATPG.
- Hands-on experience with scan insertion and scan chain implementation.
- Knowledge of fault simulation and test coverage analysis.
- Experience in DFT DRC and pattern debugging.
- Understanding of test protocols, scan compression and test modes.
- Good knowledge of Verilog and digital design fundamentals.

EDA Tools Experience with one or more of the following tools:
- Synopsys TestMAX / TetraMAX
- Siemens Tessent
- Cadence Modus

Preferred Skills
- Experience in scan compression and EDT implementation.
- Knowledge of MBIST and memory test methodologies.
- Exposure to boundary scan (JTAG / IEEE 1149.1).
- Understanding of OCC (On-Chip Clock Controller).
- Experience with advanced technology nodes.
- Knowledge of Tcl, Perl or Python scripting.
- Exposure to ATPG pattern validation and silicon bring-up.

Education B.E./B.Tech/M.Tech in Electronics, Electrical Engineering, VLSI or a related discipline.

📌 DFT Engineer (Hyderabad)
🏢 leadIC Design
📍 Hyderabad