Company Description BITSILICA is a leading Semiconductor Design Services company delivering end-to-end Concept-to-Silicon-to-Software solutions for global semiconductor clients. With a team of over 500 engineers across India, Singapore, USA, Malaysia, and Vietnam, the company focuses on innovation in semiconductor and embedded software, working on complex and cutting-edge technologies. Its pre-silicon expertise spans low-power design, IP/Subsystem/SoC design and integration, functional verification, DFT, physical design, and STA.

BITSILICA’s teams work on advanced domains including PCIe, CXL, DDR, HBM, Ethernet, USB, high-performance processors, and AI/5G/IoT/mobile SoCs, as well as embedded software, firmware, and Linux kernel/device driver development. Guided by seasoned industry leaders, BITSILICA takes full ownership of complex SoC designs, offering high-end solutions and long-term growth opportunities for engineering talent.

Role Description As a DFT Lead at BITSILICA, you will oversee Design for Testability strategy and implementation for complex SoC and IP designs, ensuring robust test coverage and manufacturability. You will define DFT architecture, select appropriate test methodologies (scan, BIST, boundary scan, compression), and guide the integration of DFT logic into RTL and physical design flows. Daily activities include collaborating with front-end and back-end design teams,



generating and reviewing test plans, running ATPG, analyzing fault coverage, and driving pattern optimization for yield and cost targets.

You will lead issue debug across silicon, simulation, and emulation environments, mentor junior DFT engineers, and contribute to methodology improvements and best practices. This is a full time, on-site role located in Bengaluru South.

Qualifications

- Strong DFT expertise, including scan insertion, ATPG, memory BIST, logic BIST, boundary scan, and test compression for complex SoCs and IPs.
- Solid front-end design skills, such as RTL design and integration, understanding of low-power design techniques, and familiarity with verification flows.
- Experience with physical design and timing aspects related to DFT, including constraints, STA considerations, and impact on area, power, and performance.
- Proficiency with industry-standard EDA tools for DFT, ATPG, simulation, and debug (e.g., Synopsys, Cadence, Siemens/Mentor toolchains).
- Capability to lead projects and teams, including task planning, technical mentoring, code and methodology reviews, and cross-functional coordination.
- Strong analytical and problem-solving skills, with the ability to debug complex test, coverage, and silicon issues and drive data-based decisions.
- Effective written and verbal

📌 DFT Lead (Bengaluru)
🏢 BITSILICA
📍 Bengaluru