Job Summary

We are seeking a Memory Timing & Power Characterization Engineer responsible for detailed analysis, modeling, and validation of timing and power characteristics of embedded memory/IPs (SRAM, NVM, etc.). The role involves working closely with design, circuit, PDK, and product teams to ensure high-performance and low-power memory solutions across PVT corners.

Key Responsibilities

Timing Characterization
Perform timing characterization (setup/hold, access time, cycle time, pulse widths) for memory IPs
Generate and validate timing models (.lib, CCS) across all corners (PVT variations)
Perform path analysis and debugging for timing failures
Support STA teams with accurate timing models and insights

Power Characterization
Perform dynamic and leakage power characterization
Generate power models (.lib) including:
Internal power
Switching power
Standby/leakage power
Analyze low-power modes (retention, sleep, deep-sleep, DVFS scenarios)

Simulation & Characterization Flow
Setup and maintain characterization settings using EDA tools (e.g., Cadence Liberate, Synopsys SiliconSmart)
Develop and maintain automation scripts (Python, Perl, Shell) for flow optimization
Work on SPICE simulations (HSPICE, Spectre, XA) for accurate results

Quality & Validation




Ensure accuracy and consistency of generated .lib models
Validate model correlation with SPICE/golden simulations
Debug characterization issues such as:
Convergence failures
Waveform inconsistencies
Model mismatches

Skill Requirements

Technical Skills
Solid understanding of:
Digital timing fundamentals (setup, hold, skew, slack)
Memory architecture (SRAM basics)
Experience in:
Timing & power characterization tools
Synopsys SiliconSmart
Cadence Liberate / Liberate MX
SPICE simulators (HSPICE, Spectre, XA)
Knowledge of PVT corners, OCV, derating, variation
Familiarity with Liberty format (.lib), CCS models
Understanding of low-power design techniques

Programming/Scripting
Proficiency in:
Python / Perl / Shell scripting

Experience in automation and flow development

Must Have Skill

Memory characterization

Valuable to Have Skill

Other Requirements

Nice to Have
Silicon correlation & post-silicon debug experience
Knowledge of advanced nodes (7nm, 5nm, below)
Familiarity with EM/IR, reliability, aging analysis
Experience with memory compiler flows

3–5 Years
Hands-on execution of characterization runs
Basic debugging of tool/setup issues
Familiar with .lib generation and validation

📌 Senior Designer Bengaluru
🏢 HCLTech
📍 Bengaluru