10 Nov
|
Tech Andhra
|
Hyderabad
10 Nov
Tech Andhra
Hyderabad
Design Implemenation:
RTL Synthesis to achieve the best Performance/Power/Area of the designs - Design Compiler, Fusion Compiler, Genus.
Setup Timing Constraints for functional and Test Modes.
Verify Logic Equivalency Checks between RTL to Gates and Gates to Gates - Conformal.
Setup signoff Static Timing Analysis and ECO flows and achieve timing closure working with the Design/DFT/PD teams.
Timing analysis with STA tools - PrimeTime, Tempus
Constraints debug and sanity checks.
Required Skills:
RTL Synthesis
STA and Timing closure
LEC (Logic and Equivalence Check)
SDC Constraints
Pay: ₹1,000,000.00 - ₹1,300,000.00 per year
Work Location: In person
📌 Rtl Design Engineer Hyderabad
🏢 Tech Andhra
📍 Hyderabad