Memory Circuit Design Engineer DRAM Circuit Design & Simulation Debug

Location: Hyderabad, Telangana
Experience: 2+ Years
Work Schedule: 5 Days per Week

1. Role Overview

We are seeking a Memory Circuit Design Engineer with hands-on experience in DRAM circuit analysis, SPICE simulation, waveform debugging, and circuit-level failure investigation.

The role involves analyzing CMOS and memory circuits, debugging simulation failures, evaluating timing and parasitic effects, and performing root cause analysis of DRAM read/write operations.

The engineer will also develop scripting-based automation to improve simulation analysis, netlist tracing, and debugging efficiency.

2. Key Responsibilities

- Analyze and debug CMOS circuits, including NMOS and PMOS transistor behavior, device characteristics, and circuit functionality.

- Perform DRAM circuit analysis covering read/write operations, sense amplifiers, memory arrays, refresh, and retention behavior.

- Interpret and debug complex SPICE netlists, including subcircuits (.SUBCKT), transistor models, device parameters, and circuit connectivity.

- Execute circuit simulations using HSPICE, Cadence Spectre, Synopsys Prime Sim, or equivalent SPICE simulation tools.

- Perform DC, transient, PVT corner, Monte Carlo, and process variation analysis to evaluate circuit performance.

- Analyze voltage and current waveforms to identify functional failures, timing violations, signal integrity issues, and abnormal circuit behavior.

- Investigate simulation failures involving floating nodes, short circuits, missing devices, incorrect transistor sizing, and convergence issues.





- Perform root cause analysis of DRAM read/write failures, sense amplifier malfunction, timing failures, and retention-related issues.

- Analyze RC parasitics, SPEF/DSPF extracted netlists, and post-layout simulation results to identify performance degradation.

- Evaluate circuit delays, timing-critical paths, and timing correlation between schematic-level and extracted simulations.

- Develop Python, Perl, and Shell scripts for simulation log parsing, netlist tracing, report generation, and automated failure classification.

- Collaborate with circuit design, verification, and layout teams to resolve design issues and improve circuit performance and reliability.

3. Required Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, VLSI, Microelectronics, or a related discipline.

- Minimum 2 years of relevant experience in memory circuit design, circuit simulation, or transistor-level debugging.

- Robust understanding of CMOS fundamentals, transistor-level circuit operation, and semiconductor device behavior.

- Practical knowledge of DRAM architecture, memory circuit functionality, and read/write operations.

- Hands-on experience with SPICE simulation tools such as HSPICE, Spectre, or Prime Sim.

- Experience in SPICE netlist analysis,



waveform debugging, and circuit failure investigation.

- Knowledge of parasitic effects, RC delay, timing analysis, and simulation methodologies.

- Scripting experience using Python, Perl, or Shell for automation and debugging support.

4. Technical Skills

A. Memory Circuit Design & Debugging

- DRAM Circuit Analysis

- DRAM Read/Write Operations

- Sense Amplifier Debugging

- Memory Array Analysis

- DRAM Refresh and Retention

- Memory Circuit Failure Analysis

B. CMOS & Transistor-Level Circuit Analysis

- CMOS Circuit Design

- NMOS/PMOS Device Characteristics

- Transistor-Level Debugging

- Digital and Analog Circuit Fundamentals

- Circuit Timing and Delay Analysis

C. SPICE Simulation & Netlist Debugging

- HSPICE / Cadence Spectre / Synopsys Prime Sim

- SPICE Netlist Analysis

- .SUBCKT Hierarchy and Connectivity Tracing

- DC and Transient Simulation

- PVT Corner and Monte Carlo Analysis

- Simulation Convergence Debugging

D. Waveform & Failure Analysis

- Voltage and Current Waveform Analysis

- Waveform Debugging

- Root Cause Analysis (RCA)

- Timing Failure Debugging

- Signal Tracing and Delay Measurement

- Circuit-Level Failure Investigation

E. Parasitic & Post-Layout Analysis

- RC Parasitic Analysis

- SPEF/DSPF Netlist Analysis

- Post-Layout Simulation

- Parasitic Extraction Fundamentals

- Timing Correlation and Delay Analysis

F. Scripting & Automation

- Python Scripting

- Perl Scripting

- Shell Scripting

- Simulation Log Parsing

- Automated Netlist Tracing

- Debug Report Generation

#LI-SD1

📌 Memory Circuit Design Engineer – DRAM Circuit Design & Simulation Debug (India)
🏢 Best NanoTech
📍 India