11 Nov
|
HCLTech
|
Bengaluru
Job Summary
Perform end‑to‑end physical design flow:FloorplanningPower planning (PG grid, IR)Placement & optimization
Key Responsibilities
TS (Clock Tree Synthesis)RoutingPost‑route optimizationAchieve timing closure across all modes and cornersResolve DRC, LVS, ERC and signoff violationsHandle low‑power design techniques:Multi‑Vt, Multi‑voltage (UPF)
Skill Requirements
Power gating, clock gatingPerform physical verification and signoff:STA (Primetime)SI / CrosstalkIR drop & EM analysisWork on advanced nodes (7nm, 5nm, 3nm or below)Collaborate with:RTL & Micro‑architecture teams
Must Have Skill
Physical Design
Valuable to Have Skill
Other Requirements
DFT & Test engineersFoundry and CAD teamsDebug complex timing, congestion, power, and variability issuesDrive methodology improvements and automation (scripts/flows)
📌 Technical Architect (Bengaluru)
🏢 HCLTech
📍 Bengaluru