11 Nov
|
smartsoc solutions
|
Bengaluru
11 Nov
smartsoc solutions
Bengaluru
Experience in verification using UVM with 3–8 years of relevant experience. Required
Skills:
Robust knowledge of SystemVerilog and UVM (SV-UVM) Strong familiarity with the AXI protocol (ACE protocol experience is a plus) Cache and coherency verification experience is a plus
Key Responsibilities
Develop sequence-based test cases from test plans using UVM-based VIPs Write test cases for UVM-based testbenches Execute test plans and develop tests in Assembly and SystemVerilog Debug test cases, test failures, and functional issues Analyze, write, and debug code and functional coverage Develop and debug functional coverage, including SV coverpoints, Improve and close code coverage gaps Work closely with overseas design teams and follow through on bug fixes Technical
Experience:
ARM v8 and v7 cores CMN, GIC, SMMU, and CoreSight Low-speed peripherals RISC-V coress, DDR, Ethernet, PCle, eMMC Low-power verification (UPF)
📌 Design Verification Engineer (Bengaluru)
🏢 smartsoc solutions
📍 Bengaluru