JOB DESCRIPTION RF Engineer Signal Processing, FPGA and RF Localization

Location:
New Delhi Employment Type: Full Time Experience Level: 3+ Years Department: Engineering / RF and Signal Processing Role Purpose The engineer will turn RF sensing requirements into a working multi receiver system that detects and localizes RF sources using time difference of arrival (TDOA). The position requires practical ownership from signal chain design and receiver synchronization through low latency DSP, FPGA firmware, source position estimation, and verification through laboratory and field measurements. Key Responsibilities ● SDR system design: Select and configure SDR platforms, RF front ends, sampling rates, bandwidths, gain settings, filtering, and I/Q capture paths for the required signals. ● Digital signal processing: Develop detection, filtering, channelization, resampling, correlation, spectral analysis, and signal quality estimation algorithms. ● Receiver synchronization: Align distributed receivers with suitable frequency and time references; characterize clock drift, timestamp uncertainty, calibration offsets, and transport delay. ● TDOA localization: Estimate time differences from captured signals, resolve ambiguous correlations, solve for source position, and report confidence and geometry related limits. ● Real time processing: Build efficient streaming pipelines for high rate I/Q data with controlled buffering, loss detection, latency, memory use, and CPU or accelerator load. ● FPGA firmware: Develop and validate FPGA logic for SDR data paths, including sample capture, timestamping, digital downconversion, filtering, decimation, DMA, and host interfaces. ● System integration: Connect receivers, FPGA logic, host software, networking, timing sources, storage, visualization, and control interfaces into a reliable sensing system. ● Test and calibration: Create repeatable tests using signal generators, known transmitters, recorded I/Q data, simulation,



and field measurements; compare estimates with ground truth. ● Engineering delivery: Maintain schematics and interface assumptions, code and HDL reviews, versioned builds, performance reports, calibration records, and release documentation. ● Cross functional support: Work with RF hardware, embedded software, FPGA, and field test teams to trace errors across the complete signal and timing path. Requirements Core Technical Areas Area Expected Knowledge and Application RF fundamentals Receiver noise figure, dynamic range, gain, filters, antennas, interference, propagation, multipath, and practical spectrum measurement. DSP Complex sampling, Fourier analysis, filtering, decimation, detection thresholds, cross correlation, spectral estimation, and fixed point effects. SDR platforms RF transceiver configuration, I/Q streaming, sample formats, clocking, calibration, driver APIs, and recorded data replay. Timing and sync Shared references or disciplined clocks, PPS or equivalent timing, timestamp alignment, drift compensation, and error budget analysis. TDOA estimation Correlation peak selection, wideband delay estimation, outlier rejection, sensor geometry, multilateration, uncertainty, and performance under multipath. FPGA development Verilog, VHDL, or SystemVerilog; pipelined DSP, timing closure, clock domain crossing, memory use, AXI or equivalent buses, and simulation. Real time software C++ or C for low latency pipelines, Python for analysis and tooling, concurrency, backpressure, profiling, and stable data interfaces. Verification Signal generators, oscilloscopes, spectrum analyzers, logic analyzers,



FPGA test benches, I/Q datasets, and ground truth field tests. Required Qualifications ● Bachelor's degree or equivalent practical experience in Electronics, Telecommunications, Electrical Engineering, Signal Processing, Computer Engineering, or a closely related discipline. ● At least 3 years of hands on experience with SDR hardware and development of DSP algorithms for sampled RF signals. ● Experience designing or implementing real time I/Q data acquisition and processing under bandwidth, latency, and compute constraints. ● FPGA development experience, including HDL design, simulation, hardware debugging, and timing closure for streaming data paths. ● Understanding of time synchronization and its effect on TDOA estimation and RF source localization. ● Robust C or C++ programming ability, practical Python for analysis and test automation, and disciplined use of Git and technical documentation. ● Ability to diagnose system errors across RF hardware, clocks, FPGA logic, software, networking, and measurement setup. Preferred Experience ● Development of multi receiver TDOA, multilateration, direction finding, spectrum monitoring, or passive RF sensing systems. ● Use of GNU Radio, UHD, SoapySDR, or vendor SDR SDKs; familiarity with Linux device interfaces and embedded deployment. ● DSP implementation on FPGA or SoC platforms, including digital downconversion, high throughput DMA, fixed point optimization, and hardware software partitioning. ● Experience with GNSS disciplined oscillators, PPS timing, PTP or other network time methods, and distributed sensor calibration. ● Statistical estimation, tracking, confidence metrics, sensor fusion, or robust localization in multipath and low signal to noise conditions. ● Deployment of distributed RF systems in field conditions, including reliable networking, remote diagnostics, and repeatable calibration procedures.

📌 RF Engineer (Delhi)
🏢 7RD
📍 Delhi