Senior Rtl Design Engineer (Hyderabad)

Senior Rtl Design Engineer (Hyderabad)

11 Nov
|
Scaledge
|
Hyderabad

11 Nov

Scaledge

Hyderabad

Job Title: RTL Design Engineer
Experience: 4 - 10 Years
Location: Bangalore, Hyderabad, Ahmedabad, Bhubaneswar, Pune, Noida.
Domain: VLSI / ASIC Design

Job Overview

We are looking for an experienced RTL Design Engineer with strong expertise in RTL coding, microarchitecture, and digital design. The candidate should have hands-on experience in RTL development using Verilog/SystemVerilog and a positive understanding of high-speed communication protocols such as PCIe, Ethernet, and AMBA.

Key Responsibilities

- Design, develop, and implement RTL for complex digital designs.
- Perform RTL coding using Verilog and SystemVerilog.
- Develop and implement microarchitecture specifications.
- Work on block-level and subsystem-level RTL design.
- Implement and integrate protocol-based IPs such as PCIe, Ethernet, and AMBA.
- Collaborate with architecture, verification, and physical design teams.
- Perform RTL debugging, code reviews, and design optimization.
- Ensure RTL quality through linting, synthesis, and design verification.
- Optimize RTL for Power, Performance, and Area (PPA).
- Participate in design reviews and technical discussions.




- Develop design documentation and microarchitecture specifications.

Required Skills

- Strong experience in RTL coding using Verilog/SystemVerilog.
- Good understanding of digital design fundamentals.
- Hands-on experience in microarchitecture development.
- Knowledge of FSM, pipelining, datapath design, and control logic.
- Experience with communication protocols such as:
- PCIe (PCI Express)
- Ethernet
- AMBA (AXI, AHB, APB)

- Understanding of ASIC design flow.
- Experience with RTL simulation, debugging, and synthesis.
- Knowledge of timing constraints and PPA optimization.
- Strong analytical and problem-solving skills.

Preferred Skills

- Experience in high-speed interface protocol design.
- Knowledge of CDC and RDC.
- Experience with RTL linting and synthesis tools.
- Familiarity with Design Verification methodologies.
- Experience with industry-standard EDA tools.

Education

- Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, VLSI, or a related field.

📌 Senior Rtl Design Engineer (Hyderabad)
🏢 Scaledge
📍 Hyderabad

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