Senior Memory Layout Engineer

Location: Bengaluru

Experience: 4–8 Years

Role Overview

We are looking for a skilled Senior Memory Layout Engineer with strong hands-on experience in SRAM layout design and custom layout development across advanced technology nodes. The ideal candidate should have expertise in FinFET technologies, lower-node layout challenges and memory circuit layout implementation at 2nm, 3nm and 5nm nodes.

Key Responsibilities

- Own and execute full-custom SRAM layout design for advanced semiconductor technologies.
- Develop and optimize memory layouts across FinFET-based technology nodes.
- Work on SRAM bitcell, array, peripheral circuits and memory compiler-related layouts.
- Handle layout implementation, floorplanning, placement and routing of memory blocks.
- Ensure DRC, LVS, ERC and physical verification signoff.
- Drive layout optimization for area, power, performance and manufacturability.
- Work closely with SRAM Circuit Design, Custom Design, Foundry and Physical Verification teams.
- Resolve complex layout issues associated with advanced technology nodes.
- Support layout migration and technology scaling across 5nm, 3nm and 2nm nodes.




- Ensure adherence to foundry design rules and advanced-node layout requirements.

Required Technical Skills

- 4–8 years of experience in Custom IC / Memory Layout Design.
- Strong hands-on experience in SRAM Layout Design.
- Expertise in FinFET technology and advanced-node layout methodologies.
- Exposure to 2nm, 3nm and 5nm technology nodes.
- Robust understanding of SRAM bitcell, memory arrays and peripheral circuit layouts.
- Hands-on experience with DRC, LVS and physical verification.
- Proficiency in industry-standard custom layout tools (Cadence Virtuoso preferred).
- Good understanding of matching, symmetry, parasitic effects and layout-dependent effects.
- Experience working with foundry PDKs and advanced-node design rules.

Preferred Qualifications

- BE/BTech/MTech in Electronics, Electrical or VLSI-related disciplines.
- Experience in high-density SRAM macros and advanced memory architectures.
- Exposure to FinFET layout challenges and lower-node technology migration.
- Strong debugging, problem-solving and cross-functional collaboration skills.

📌 Senior Memory Layout Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru