Own, maintain, debug, and enhance DDR initialization and training firmware for Microchip FPGA platforms. Ensure reliable DDR bring-up across supported memory configurations and board designs.

Key Responsibilities

- Develop, maintain, and enhance DDR training and initialization code for Microchip FPGA devices.
- Debug DDR training failures, timing/calibration issues, and memory initialization problems on hardware.
- Collaborate with silicon, hardware design, validation, and characterization teams to root-cause DDR issues.
- Develop and maintain diagnostic utilities, test cases, and regression tests for DDR reliability.
- Support new DDR configurations, silicon revisions, silicon families, and platform releases.

Required Skills

- Solid C programming and embedded firmware debugging skills.




- Good understanding of DDR3/DDR4/LPDDR4/DDR5/LPDDR5 memory interfaces, initialization, training, and timing parameters.
- Experience with bare-metal firmware, low-level register programming, proprietary systems, RISC-V SoCs, and high-speed peripherals.
- Hands-on experience debugging hardware/software issues using JTAG debuggers, oscilloscopes, or logic analyzers.
- Ability to analyze technical specifications, schematics, and timing requirements.
- Preferred: Experience with DDR PHY/controller integration, RISC-V SoCs, FPGA-based SoC platforms, and memory signal-integrity analysis.

📌 Senior Embedded Software Engineer (Hyderabad)
🏢 Leadsoc Technologies
📍 Hyderabad